`timescale    1ns/100ps
module sys_comm#(
parameter [31:0] VERSION_DATE     =  32'h19_07_08_16,
parameter [7:0]  MAIN_FUNCTION    =  "S",
parameter [7:0]  SUB_FUNCTION     =  "A",
parameter [7:0]  MAIN_SOLUTION    =  1,
parameter [7:0]  SUB_SOLUTION     =  2,
parameter [7:0]  APPLICATION_TYPE =  "G",
parameter [7:0]  MAIN_VERSION     =  1,
parameter [7:0]  SUB_VERSION      =  0,
parameter [7:0]  MINI_VERSION     =  0,

parameter        DEVICE_TYPE      =  0,
parameter [23:0] FLASH_BIAS       =  24'hB1CE6

)
(
    //复位&时钟&同步
    input       wire            resetb      ,
    input       wire            sclk        , //125m
    input       wire            time_1ms_sync   ,
    input       wire            time_1s_sync    ,
    input       wire            time_15ms_sync  ,
    input       wire            time_250ms_sync ,
    
    input       wire            sclkin      ,  //25m//用途？？
    input       wire            clk_mcu     , //62.5m//内部处理
    
    //JTAG
    input       wire            JTCK        ,
    input       wire            JTRST_n     ,	//内部屏蔽
    input       wire            JTDI        ,
    input       wire            JTMS        ,
    output      wire            JTDO        ,
    
    //MCU工作状态
    output	wire		mcu_init_flag,	//MCU复位标志
    output	wire		mcu_ctrl_flag,	//MCU控制标志
    //复位状态
    output      wire            init_mode       ,
    output      wire            comm_en         ,
    
    output      wire            flash_SCK   ,	//内部双向处理
    output      wire            flash_CS_n  ,
    
    output      wire            FLASH_IO0_SI,
    input       wire            FLASH_IO0_SI_i  ,
    output      wire            FLASH_SI_OE ,

    output      wire            FLASH_IO1_SO,
    input       wire            FLASH_IO1_SO_i  ,
    output      wire            FLASH_SO_OE ,
    
    //PHY控制信号
    output      wire            phy_rst_mcu     ,
    output      wire            mdc             ,
    inout       tri             mdio            ,
        
    //通讯接口
    input       wire            rec_flag    ,
    input       wire            rec_error   ,
    input       wire [7:0]      rec_data    ,
    input       wire [1:0]      rec_vendor  , //0:无效包 1：UDP包
    input       wire            blank_flag  ,
    input       wire            redu_flag   ,
    input       wire [1:0]      gp0_rx_type ,
    input       wire [1:0]      gp1_rx_type ,
    
    output      wire            send_flag   ,
    output      wire            pre_flag    ,
    output      wire [7:0]      send_data   ,
        
    //配置总线
    output      wire            set_d_ok        ,
    output      wire [30:0]     set_addr        ,
    output      wire [31:0]     set_data        ,
    input       wire [31:0]     rd_data        ,
        
    //锁定处理
    output	wire		lock_enable,    
    
    output      wire [31:0]     lock        ,//MCU处理显示显示设置包，或通过总线传送
    input       wire            locked      ,
    
    //PLL处理
    input       wire [3:0]      pll_reset_cnt   ,//通过总线传送？？
    
    output      wire            reconfig_pll_en ,
        
    //按键输入
    input       wire            key_in          ,
    
    input       wire            frame_start     ,//通过总线传送？？？
    output      wire            key_out         ,
    
    output      wire [9:0]      ram_waddr_rgb   ,
    output      wire [31:0]     ram_wdata_rgb   ,
    output      wire            ram_wr_rgb      ,
    input       wire            kp_busy         ,
        
    //sdram读写，移至SDRAM处    
    input       wire            sdram_ready ,
    output      wire [31:0]     sdram_ram_data_w        ,
    input       wire [31:0]     sdram_ram_data_r        ,
    output      wire [ 9:0]     sdram_ram_addr          ,
    output      wire            sdram_ram_addr_wren     ,
        
    output      wire [23:0]     sdram_addr_start        ,
    output      wire            sdram_wr_or_rd          ,
    output      wire            sdram_req               ,
    input       wire            sdram_busy              ,
    output      wire [10:0]     sdram_rw_len            
   

);

//**************************************************************
//        通讯数据处理/上电初始化
//**************************************************************


// tri     [7:0]       GPIO0           ;
// tri     [7:0]       GPIO1           ;
// tri     [7:0]       GPIO2           ;
wire [7:0]  GPIO0_I              ;
wire [7:0]  GPIO0_O              ;
wire [7:0]  nGPEN0               ;
wire [7:0]  GPIO1_I              ;
wire [7:0]  GPIO1_O              ;
wire [7:0]  nGPEN1               ;
wire [7:0]  GPIO2_I              ;
wire [7:0]  GPIO2_O              ;
wire [7:0]  nGPEN2               ;

    
wire                O_INI_IP        ;
    
wire                EXT_RAM_EN      ;
wire                EXT_RAM_WR      ;
wire    [3:0]       EXT_RAM_BYTE_EN ;
wire    [13:0]      EXT_RAM_ADDR    ;
wire    [31:0]      EXT_RAM_WDATA   ;
wire    [31:0]      EXT_RAM_RDATA   ;

wire [3:0]       apb_sel            ;
wire [31:0]      apb_addr           ;
wire             apb_rw_en          ;
wire [3:0]       apb_byteena        ;
wire [31:0]      apb_wdata          ;
wire [31:0]      apb_rdata          ;

wire                reboot_en       ;

wire                packet_load     ;
wire                fpga_rec_flag   ;
wire                mcu_rec_end     ;
wire    [1:0]       fpga_flag_next  ;


wire    [7:0]       state_data      ;

wire                id_is_valid     ;
wire    [63:0]      id              ;

wire reboot_o_osc;
reg  [ 11: 0] reboot_en_cnt;
reg  reboot_en_delayed;
wire [1:0]  reboot_sel;
///////////////////////////////////////////////////////////////
mcu_top #(
    .FLASH_BIAS (   FLASH_BIAS  )
)
mcu_top
(
    .sclk                   (   sclk                        ),
    .clk_mcu                (   clk_mcu                     ),
    .resetb                 (   resetb                      ),

    .UART_RXD               (                               ),
    .UART_CTS_n             (                               ),
    .UART_TXD               (                               ),
    .UART_RTS_n             (                               ),

    .JTRST_n                (   1'b1                        ),
    .JTCK                   (   JTCK                        ),
    .JTDI                   (   JTDI                        ),
    .JTMS                   (   JTMS                        ),
    .JTDO                   (   JTDO                        ),

    .EXT_RAM_EN             (   EXT_RAM_EN                  ),
    .EXT_RAM_WR             (   EXT_RAM_WR                  ),
    .EXT_RAM_ADDR           (   EXT_RAM_ADDR                ),
    .EXT_RAM_BYTE_EN        (   EXT_RAM_BYTE_EN             ),
    .EXT_RAM_WDATA          (   EXT_RAM_WDATA               ),
    .EXT_RAM_RDATA          (   EXT_RAM_RDATA               ),


    .FLASH_SCK              (   flash_SCK                   ),
    .FLASH_CS_N             (   flash_CS_n                  ),
    
    .FLASH_IO0_SI           (   FLASH_IO0_SI                ),
    .FLASH_IO0_SI_i         (   FLASH_IO0_SI_i              ),
    .FLASH_SI_OE            (   FLASH_SI_OE                 ),

    .FLASH_IO1_SO           (   FLASH_IO1_SO                ),
    .FLASH_IO1_SO_i         (   FLASH_IO1_SO_i              ),
    .FLASH_SO_OE            (   FLASH_SO_OE                 ),
    

    // .GPIO0                  (   GPIO0                       ),
    // .GPIO1                  (   GPIO1                       ),
    // .GPIO2                  (   GPIO2                       ),
    
    .GPIO0_I                ( GPIO0_I          ),
    .GPIO0_O                ( GPIO0_O          ),
    .nGPEN0                 ( nGPEN0           ),
    .GPIO1_I                ( GPIO1_I          ),
    .GPIO1_O                ( GPIO1_O          ),
    .nGPEN1                 ( nGPEN1           ),
    .GPIO2_I                ( GPIO2_I          ),
    .GPIO2_O                ( GPIO2_O          ),
    .nGPEN2                 (   nGPEN2                      ),
    .O_INI_IP               (   O_INI_IP                    ),
    
    
    .apb_sel                (   apb_sel                     ),
    .apb_addr               (   apb_addr                    ),
    .apb_rw_en              (   apb_rw_en                   ),
    .apb_byteena            (   apb_byteena                 ),
    .apb_wdata              (   apb_wdata                   ),
    .apb_rdata0             (   apb_rdata0                  ),
    .apb_rdata1             (   apb_rdata1                  ),
    .apb_rdata2             (   apb_rdata2                  ),
    .apb_rdata3             (   apb_rdata3                  )
) ;

v8_com_ctrl_mcu_04
#(
    .DEVICE_TYPE(DEVICE_TYPE)
) com_ctrl(

    .resetb                 (   resetb                              ),
    .sclk                   (   sclk                                ),
    .comm_en                (   comm_en                             ),

    .rec_flag               (   rec_flag                            ),
    .rec_error              (   rec_error                           ),
    .rec_data               (   rec_data                            ),
    .rec_vendor             (   rec_vendor                          ),

    .send_flag              (   send_flag                           ),
    .pre_flag               (   pre_flag                            ),
    .send_data              (   send_data                           ),

    .blank_flag             (   blank_flag                          ),
    .redu_flag              (   redu_flag                           ),
    .time_1ms_sync          (   time_1ms_sync                       ),

    .clk_mcu                (   clk_mcu                             ), //62.5M

    .EXT_RAM_EN             (   EXT_RAM_EN                          ),
    .EXT_RAM_WR             (   EXT_RAM_WR                          ),
    .EXT_RAM_BYTE_EN        (   EXT_RAM_BYTE_EN                     ),
    .EXT_RAM_ADDR           (   EXT_RAM_ADDR                        ),
    .EXT_RAM_WDATA          (   EXT_RAM_WDATA                       ),
    .EXT_RAM_RDATA          (   EXT_RAM_RDATA                       ),

    .packet_load            (   packet_load                         ),
    .interrupt              (   fpga_rec_flag                       ),

    .mcu_rec_end            (   mcu_rec_end                         ),
    .fpga_flag_next         (   fpga_flag_next                      )
    );


//显示设置接口	：不需要
display_bus_02 display_bus(
    //复位，时钟，工作使能
    .resetb                 (   resetb                                  ),
    .sclk                   (   sclk                                    ),
    .clk_mcu                (   clk_mcu                                 ),
    .sclkin                 (   sclkin                                  ),
    .time_1s                (   time_1s_sync                            ),
    .time_15ms              (   time_15ms_sync                          ),
    .time_250ms             (   time_250ms_sync                         ), //(t_s),

    .apb_sel                (   apb_sel                     ),
    .apb_addr               (   apb_addr                    ),
    .apb_rw_en              (   apb_rw_en                   ),
    .apb_byteena            (   apb_byteena                 ),
    .apb_wdata              (   apb_wdata                   ),
    .apb_rdata0             (   apb_rdata0                   ),
    .apb_rdata1             (   apb_rdata1                   ),
    .apb_rdata2             (   apb_rdata2                   ),
    .apb_rdata3             (   apb_rdata3                   ),
    
    // .GPIO0                  (   GPIO0                                 ),
    // .GPIO1                  (   GPIO1                                 ),
    // .GPIO2                  (   GPIO2                                 ),
    
    .GPIO0_I                ( GPIO0_I          ),
    .GPIO0_O                ( GPIO0_O          ),
    .nGPEN0                 ( nGPEN0           ),
    .GPIO1_I                ( GPIO1_I          ),
    .GPIO1_O                ( GPIO1_O          ),
    .nGPEN1                 ( nGPEN1           ),
    .GPIO2_I                ( GPIO2_I          ),
    .GPIO2_O                ( GPIO2_O          ),
    .nGPEN2                 (   nGPEN2                                  ),

    .interrupt              (   fpga_rec_flag               ),

    .mcu_rec_end            (   mcu_rec_end                 ),
    .fpga_flag_next         (   fpga_flag_next              ),

    /****************phy *******************/
    .PHY_RST_N              (   phy_rst_mcu                 ),
    .PHY_MDC                (   mdc                         ),
    .PHY_MDIO               (   mdio                        ),
    //内部寄存器设置总线
    .set_d_ok               (   set_d_ok                    ),
    .set_addr               (   set_addr                    ),
    .set_data               (   set_data                    ),
    //读取返回数据的接口
    .sys_state_data         (   state_data                  ),

    // .id_is_valid            (   id_is_valid                 ),
    // .id                     (   id                          ),

    //
    .lock_enable            (   lock_enable                 ),
    .lock                   (   lock                        ),


    //逐点调整数据
    .I_sdram_ready          (   sdram_ready                 ),

    // .O_sdram_refresh_en  (   sdram_refresh_en            ),


    .init_mode              (   init_mode                   ),
    .reboot_en              (   reboot_en                   ),
    .comm_en                (   comm_en                     ),

    .reboot_sel             (   reboot_sel                  ),
    .reconfig_pll_en        (   reconfig_pll_en             ),

    .frame_start            (   frame_start                 ),
    //按键
    .key_in                 (   key_in                      ),
    
    
    .key_out                (   key_out                     ),

    .ram_waddr_rgb          (   ram_waddr_rgb               ),
    .ram_wdata_rgb          (   ram_wdata_rgb               ),
    .ram_wr_rgb             (   ram_wr_rgb                  ),
    .kp_busy                (   kp_busy                     ),

    .sdram_ram_data_w       (   sdram_ram_data_w            ),
    .sdram_ram_data_r       (   sdram_ram_data_r            ),
    .sdram_ram_addr         (   sdram_ram_addr              ),
    .sdram_ram_addr_wren    (   sdram_ram_addr_wren         ),

    .sdram_addr_start       (   sdram_addr_start            ),
    .sdram_wr_or_rd         (   sdram_wr_or_rd              ),
    .sdram_req              (   sdram_req                   ),
    .sdram_busy             (   sdram_busy                  ),
    .sdram_rw_len           (   sdram_rw_len                )

    );

//系统状态数据生成
state_ctrl_02
#(
    .MAIN_FUNCTION    (MAIN_FUNCTION   ),
    .SUB_FUNCTION     (SUB_FUNCTION    ),
    .MAIN_SOLUTION    (MAIN_SOLUTION   ),
    .SUB_SOLUTION     (SUB_SOLUTION    ),
    .APPLICATION_TYPE (APPLICATION_TYPE),
    .MAIN_VERSION     (MAIN_VERSION    ),
    .SUB_VERSION      (SUB_VERSION     ),
    .MINI_VERSION     (MINI_VERSION    ),
    .VERSION_DATE     (VERSION_DATE    )
) state_ctrl(
    .resetb                 (   resetb          ),
    .sclk                   (   sclk            ),

    //设置总线接口
    .packet_load            (   packet_load     ),
    .fpga_rec_flag          (   fpga_rec_flag   ),
    .ext_addr               (   16'b0           ),
    .set_addr               (   set_addr        ),
    .set_d_ok               (   set_d_ok        ),
    .set_data               (   set_data        ),

    //千兆PHY接口,包错误统计
    .rec_flag               (   rec_flag        ),
    .rec_error              (   rec_error       ),

    //
    .gp0_rx_type            (   gp0_rx_type     ),
    .gp1_rx_type            (   gp1_rx_type     ),

    //
    // .id                     (   id              ),

    //
    .lock_enable            (   lock_enable     ),
    .locked                 (   locked          ),

    .pll_reset_cnt          (   pll_reset_cnt   ),
    .phy_reset_cnt          (                   ),

    //状态寄存器
    .state_data             (   state_data      )

);




`ifdef ALTERA
`else
always @(posedge sclk)
    if (reboot_en)
        begin
        if (reboot_en_cnt != 12'hfff)
            reboot_en_cnt <= reboot_en_cnt + 1'b1;
        end
    else
        reboot_en_cnt <= 'd0;

always @(posedge sclk)
    reboot_en_delayed <= reboot_en_cnt == 12'hfff;

alta_boot reboot(
    .i_boot(reboot_en_delayed),
    .im_vector_sel(reboot_sel),
    .i_osc_enb(1'b1),
    .o_osc(reboot_o_osc) // 不能悬空
);
`endif

endmodule
`default_nettype wire